Periodically backup SVN server is a good practice. It's also useful when you want to relocate your svn server. Here are the simple steps:
1. login to the svn server
2. backup your svn repo, if more then one repo, do it one by one...
Introduction
This article is written with the target to eliminate new learner's most frequent questions: what's the difference between blocking assignment and non-blocking assignment?
Blocking Assignment
Blocking Assignment
always...
When design an FPGA based board, memory components are usually the must-have device. But how to select the most appropriate memory type among the large range of available choices is the first question the designer can have. First of all, I list...
What's SoC FPGA?
A semiconductor devices that integrate FPGA fabric, hardened CPU subsystems, and other hardened IP.
What happened in the last decade?
These SoC FPGAs complement the decade-long availability of soft-core CPUs and other...
A great document management software is released by Xilinx --- Xilinx Documentation Navigator.
As many FPGA developers known, Xilinx has extreme abundant documentations on line. New users always have difficulty to find and utilise the...
In order to make this tutorial more general, I will not focus on official supported Xilinx or Avnet FPGA development boards, but a third party board instead. It's well known that EDK is a great tool for the supported boards which you just...
Noise
Noiseis a random fluctuation in an electrical signal, a characteristic of all electronic circuits. Noise generated by electronic devices varies greatly, as it can be produced by several different effects. Thermal and shot noise are...
Users can move logic that is normally implemented with configurable logic blocks (CLB) to user-configurable input/output blocks (IOB) since FPGAs have limited logic resources in the IOBs. By moving logic from CLBs to IOBs, additional logic...
VHDL and Verilog are two main industry standard hardware description languages. It is well know that Verilog is modelled after C, and VHDL is modelled after Ada which decides they are quite different kinds of languages. This artical gives a basic...
Sequential logic
Sequential logic blocks generate the flip-flops in a design. There should be no other logic generated inside the sequential block. No delays should ever be coded into synthesizable logic, including the sequential logic block....
1. Sequential Blocks
A begin-end block is a means of grouping two or more procedural assignments together so that they act like a single group of sequential statements. Individual statements within a begin-end block are executed...
A Verilog module starts with the module keyword followed by the name of the module and the port list, which is a list of the names of all the inputs and outputs of the module. The next section contains the port declarations. module behaves...
Conventionally C++ is broadly used in high frequency trading (HFT) projects because the low development cost and good performance. However when performance is omnipotent C++ based quote stream decoding, e.g. FIX protocol is not perfect. Here...
This article will talk about how to utilise Xilinx website resource to learn Xilinx FPGA programming faster.This article will talk about how to utilise Xilinx website resource to learn Xilinx FPGA programming faster.This article will talk...
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